CY22381FI
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CY22381FI

Product Category: IC Chips
Manufacturer: CYPRESS
Description:
  datasheetCY22381FI Datasheet
Package: SOP-8
Quantity: 473 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
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Manufacturer: CYPRESS
Product Category: IC Chips
Features, Applications

Three-PLL General Purpose FLASH Programmable Clock Generator

Features 

Three integrated phase-locked loops Benefits Generates up to three unique frequencies on three outputs to 200 MHz from an external source. Functional upgrade for current CY2081 family.


Ultra-wide divide counters (eight-bit Q, eleven-bit P, and Allows for 0 ppm frequency generation and frequency seven-bit post divide) conversion under the most demanding applications. Improved linear crystal load capacitors Flash programmability Improves frequency accuracy over temperature, age, process, and initial offset. Non-volatile programming enables easy customization, ultra-fast turnaround, performance tweaking, design timing margin testing, inventory control, lower part count, and more secure product supply. Can also be programmed multiple times which reduces programming errors and provides an easy upgrade path for existing designs. In-house programming of samples and prototype quantities is available using the CY3672 FTG development Kit. Production quantities are available through Cypress's value-added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. Performance suitable for high-end multimedia, communications, industrial, A/D converters, and consumer applications. Supports numerous low-power application schemes and reduces EMI by allowing unused outputs to be turned off. Adjust crystal drive strength for compatibility with virtually all crystals. External frequency select option for PLL1, CLKA, and CLKB. Industry standard supply voltage. Industry standard packaging saves on board space. Easy-to-use software support for design entry.


Low-jitter, high-accuracy outputs Power-management options (Shutdown, OE, Suspend) Configurable crystal drive strength Frequency select option via external LVTTL Input 3.3V operation Eight-pin SOIC package CyClocks RTTM support


XTALIN XTALOUT OSC. PLL1 CONFIGURATION FLASH 8-BIT Q Divider 7-BIT CLKC

Pin Configuration CY22381 8-pin SOIC CLKC GND XTALIN XTALOUT FS/SUSPEND/OE/SHUTDOWN VDD CLKA CLKB

Part Number CY22381FC CY22381FI Outputs 3 Input Frequency Range Output Frequency Range Specifics Commercial Temperature Industrial Temperature 8 MHz - 30 MHz (external crystal) to 200 MHz 1 MHz - 166 MHz (reference clock) 8 MHz - 30 MHz (external crystal) to 166 MHz 1 MHz - 150 MHz (reference clock)


Name CLKC GND XTALIN XTALOUT CLKB CLKA VDD FS/SUSPEND/ OE/SHUTDOWN Pin Number Description Configurable clock output C Ground Reference crystal input or external reference clock input Reference crystal feedback (float if XTALIN is driven by external reference clock) Configurable clock output B Configurable clock output A Power supply General Purpose Input. Can be Frequency Control, Suspend mode control, Output Enable, or full-chip shutdown. divider in the PLL feedback loop (P). The output PLL3 is sent to the cross-point switch. General-Purpose Input The CY22381 features an output control pin (pin 8) that can be programmed to control one of four features. When programmed as a Frequency Select (FS), the input can select between two arbitrarily programmed frequency settings. The Frequency Select can change the following; the frequency of PLL1, the output divider of CLKB, and the output divider of CLKA. Any divider change as a result of switching the FS input is guaranteed to be glitch free. The general-purpose input can simultaneously control the Suspend feature, turning off a set of PLLs and outputs determined during programming. When programmed as an Output Enable (OE) the input forces all outputs to be placed in a three-state condition when LOW. When programmed as a Shutdown, the input forces a full chip shutdown mode when LOW. Crystal Input The input crystal oscillator is an important feature of this device because of its flexibility and performance features.


The is an upgrade to the existing CY2081. The new device has a wider frequency range, greater flexibility, improved performance, and incorporates many features that reduce PLL sensitivity to external system issues. The device has three PLLs that allow each output to operate at an independent frequencies. These three PLLs are completely programmable. Configurable PLLs PLL1 generates a frequency that is equal to the reference divided by an eight-bit divider (Q) and multiplied an 11-bit divider in the PLL feedback loop (P). The output PLL1 is sent to the crosspoint switch. The frequency of PLL1 can optionally be changed by using the external CMOS general purpose input. See the following section on "General-Purpose Input" for more detail. PLL2 generates a frequency that is equal to the reference divided by an eight-bit divider (Q) and multiplied an 11-bit divider in the PLL feedback loop (P). The output PLL2 is sent to the crosspoint switch. PLL3 generates a frequency that is equal to the reference divided by an eight-bit divider (Q) and multiplied an 11-bit


The oscillator inverter has programmable drive strength. This allows for maximum compatibility with crystals from various manufacturers, processes, performances, and qualities. The input load capacitors are placed on-die to reduce external component cost. These capacitors are true parallel-plate capacitors for ultra-linear performance. These were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. Non-linear (FET gate) crystal load capacitors should not be used for MPEG, POTS dial tone, communications, or other applications that are sensitive to absolute frequency requirements. The value of the load capacitors is determined by six bits in a programmable register. The load capacitance can be set with a resolution 0.375 pF for a total crystal load range to 30 pF. For driven clock inputs the input load capacitors may be completely bypassed. This enables the clock chip to accept driven frequency inputs to 166 MHz. If the application requires a driven input, then XTALOUT must be left floating. Output Configuration Under normal operation there are four internal frequency sources that may be routed via a programmable crosspoint switch to any of the three outputs via programmable seven-bit output dividers. The four sources are: reference, PLL1, PLL2, and PLL3. The following is a description of each output. CLKA's output originates from the crosspoint switch and goes through a programmable seven-bit post divider. The seven-bit post divider derives its value from one of two programmable registers controlled by FS. CLKB's output originates from the crosspoint switch and goes through a programmable seven-bit post divider. The seven-bit post divider derives its value from one of two programmable registers controlled by FS. CLKC's output originates from the crosspoint switch and goes through a programmable seven-bit post divider. The seven-bit post divider derives its value from one programmable register. The Clock outputs have been designed to drive a single point load with a total lumped load capacitance of 15 pF. While driving multiple loads is possible with the proper termination, it is generally not recommended. Power-Saving Features When configured as OE, the general-purpose input three-states all outputs when pulled LOW. When configured as Shutdown, a LOW on this pin three-states all outputs and shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins will be less than 5 μA (typical). After leaving shutdown mode, the PLLs will have to relock. When configured as SUSPEND, the general-purpose input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output forces a three-state condition. Improving Jitter Optimization Control is useful in mitigating problems related to similar clocks switching at the same moment and causing excess jitter. If one PLL is driving more than one output, the negative phase of the PLL can be selected for one of the outputs. This prevents the output edges from aligning, allowing superior jitter performance.


CyClocks RT is our second-generation application that allows users to configure this device. The easy-to-use interface offers complete control of the many features of this family including input frequency, PLL and output frequencies, and different functional options. Data sheet frequency range limitations are checked and performance tuning is automatically applied. 

Search Part number : "CY223" Included word is 15
Part Number Manufacturer Package Quantity Description
CY22392ZC-347T CYPRESS TSSOP 3430
CY22393FX CY TSSOP 3592
CY22393ZXC-551T CYPRESS TSSOP16 2066
CY22381SXC-157T CY SOP14 1074
CY22313ZC CYPRESS TSSOP-24 942
CY22393ZC-527T CYPRESS NA 495
CY22388ZXC-22T CYPRESS SSOP 5394
CY22392ZXC-386 CYPRESS TSSOP18 497
CY22392FXC-ISB-PBF-OSE CY TSSOP16 118
CY22392FXCT Cypress Semiconductor Corp 16-TSSOP (0.173", 4.40mm Width) 3560 IC CLOCK GEN PROG 16-TSSOP
CY22381SXC-158T Cypress Semiconductor Corp SOIC-8 3545 IC CLOCK GENERATOR
CY22388ZXC-24T Cypress Semiconductor Corp TSSOP16 15860 IC CLOCK GENERATOR
CY22313ZC-1 CYPRESS SSOP 3726
CY22392ZXI-374T CYPRESS TSSOP-16 3560
CY22393ZC-533T CYPRESS TSOP 718
CY22381FI RELATED PRODUCT PICTURE
left
  • CY22392ZC-347T
  • CY22393FX
  • CY22393ZXC-551T
  • CY22381SXC-157T
  • CY22313ZC
  • CY22393ZC-527T
  • CY22388ZXC-22T
  • CY22392ZXC-386
  • CY22392FXC-ISB-PBF-OSE
  • CY22392FXCT
  • CY22381SXC-158T
  • CY22388ZXC-24T
  • CY22313ZC-1
  • CY22392ZXI-374T
  • CY22393ZC-533T
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