SP8782B
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Manufacturer Part#:

SP8782B

Product Category: IC Chips
Manufacturer: ZARLINK
Description:
  datasheetSP8782B Datasheet
Package: SOP-8
Quantity: 473 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: ZARLINK
Product Category: IC Chips
Features, Applications

Features

Advanced Resynchronisation techniques to negate loop delay effects CMOS compataible output capability Multi-Modulus division Available as DESC SMD 5962-9208901MPA


Description

The is a multi-modulus divider which divides 16/ 17 when the Ratio Select input is low and by 32/33 when theRatio Select input is high. When high, the modulus Control input selects the lower division ratio or 32) and the higher ratio or 33) when it is low. The device uses resynchronisation techniques to reduce the effects of propagation delays in frequency synthesis. The SP8782A (ceramic DIL package) is characterised over the full military temperature range +125 C, the SP8782B (miniature plastic DIL package) over the industrial range to+85 C.


Supply Voltage Clock input level Junction temperature Storage temperature range: 6V 2.5V p-p +125 C

RATIO SELECT CLOCK INPUT CLOCK INPUT VEE

RATIO SELECT CLOCK INPUT CLOCK INPUT VEE VCC OUTPUT NC MODULUS CONTROL

Unless otherwise stated, the Electrical Characteristics are guaranteed over the specified supply, frequency and temperature range. Supply Voltage, VCC to +5.5V, VEE = 0V Temperature Tamb= C (SP8782B)


Maximum frequency (sinewave input) Minimum frequency Min Slew rate for low frequency operation Power Supply current, ICC Output low voltage Output high voltage Modulus control input high voltage Modulus control input low voltage Modulus control input high current Modulus control input low current Ratio select input high voltage Ratio selected input low voltage Ratio select input current Clock to output propagation Delay Set-up time, ts Release time,tr


At driver end of 3k resistor At driver end of 3k resistor Via 3k resistor to VCC Via 3k resistor to VCC


Notes: 1. The set-up time ts is defined as the minimum time that can elapse between LH transition of the modulus control input and the next LH output transition to ensure that the 16 (32) mode is obtained. 2. The release time tr is defined as the minimum time that can elapse between HL transition of the modulus control input and the next LH output transition to ensure that the 17 (33) mode is obtained.


Fig. 3a Setting divide-by-16 Figure 3a Setting divide 16 (32 mode) (32) mode

Search Part number : "SP878" Included word is 1
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SP8789 SIPEX DIP8 72
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