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Kynix Part #: KY32-MT3170BE
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Product Category: IC Chips
Manufacturer: ZARLINK
  datasheetMT3170BE Datasheet
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Manufacturer: ZARLINK
Product Category: IC Chips
Features, Applications


Wide dynamic range (50dB) DTMF Receiver Call progress (CP) detection via cadence indication 4-bit synchronous serial data output Software controlled guard time for MT3x70B Internal guard time circuitry for MT3x71B Powerdown option MT337xB) 4.194304MHz crystal or ceramic resonator (MT337xB and MT327xB) External clock input (MT317xB) Guarantees non-detection of spurious tones

Ordering Information MT3170/71BE 8 Pin Plastic DIP MT3270/71BE 8 Pin Plastic DIP MT3370/71BS 18 Pin SOIC MT3370/71BN 20 Pin SSOP +85 C signalling. The MT3x70B provides an early steering (ESt) logic output to indicate the detection of a DTMF signal and requires external software guard time to validate the DTMF digit. The MT3x71B, with preset internal guard times, uses a delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector output. In the presence of supervisory tones, the call progress detector circuit indicates the cadence (i.e., envelope) of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific call progress signals. The MT327xB and MT337xB can be used with a crystal or a ceramic resonator without additional components. A power-down option is provided for the MT317xB and MT337xB.


Integrated telephone answering machine End-to-end signalling Fax Machines


The is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end

Steering Circuit High Group Filter Antialias Filter Dial Tone Filter Low Group Filter Digital Detector Algorithm Code Converter and Latch

Digital Guard Time Parallel to Serial Converter & Latch

Pin 1 3 Name INPUT OSC2 OSC1 (CLK) Description DTMF/CP Input. Input signal must be AC coupled via capacitor. Oscillator Output. Oscillator/Clock Input. This pin can either be driven by: 1) an external digital clock with defined input logic levels. OSC2 should be left open. 2) connecting a crystal or ceramic resonator between OSC1 and OSC2 pins. Ground. (0V) Serial Data/Call Progress Output. This pin serves the dual function of being the serial data output when clock pulses are applied after validation of DTMF signal, and also indicates the cadence of call progress input. As DTMF signal lies in the same frequency band as call progress signal, this pin may toggle for DTMF input. The SD pin is at logic low in powerdown state. Acknowledge Pulse Input. After ESt or DStD is high, applying a sequence of four pulses on this pin will then shift out four bits on the SD pin, representing the decoded DTMF digit. The rising edge of the first clock is used to latch the 4-bit data prior to shifting. This pin is pulled down internally. The idle state of the ACK signal should be low. Early Steering Output. A logic high on ESt indicates that a DTMF signal is present. ESt is at logic low in powerdown state. Delayed Steering Output. A logic high on DStD indicates that a valid DTMF digit has been detected. DStD is at logic low in powerdown state. Positive Power Supply (5V Typ.) Performance of the device can be optimized by minimizing noise on the supply rails. Decoupling capacitors across VDD and VSS are therefore recommended. No Connection. Pin is unconnected internally.

Power Down Input. A logic high on this pin will power down the device to reduce power consumption. This pin is pulled down internally and can be left open if not used. ACK pin should be at logic '0' to power down device.

Summary of MT3x70/71B Product Family Device Type MT3371B 8 Pin 18 Pin 20 Pin PWDN 2 Pin OSC Ext CLK ESt DStD

The MT3x7xBs are high performance and low power consumption DTMF receivers. These devices provide wide dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following the unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output is routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to separate the input DTMF signal into high and low group tones. The high group and low group tones are then verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection stage, the valid DTMF digit is translated a 4-bit binary code (via an internal lookup ROM). Data bits can then be shifted out serially by applying external clock pulses. Automatic Gain Control (AGC) Circuit As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With large input signal amplitude (between 0 and approximately -30dBm for each tone of the composite signal), the AGC is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit. Filter and Decoder Section The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection. The composite dual-tone signal is further split into its individual high and low frequency components by two 6th order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate output filters and squared by high gain limiting comparators. The

resulting squarewave signals are applied to a digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For MT3x70B, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high, indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt pin to go low. For MT3x71B, an internal delayed steering counter validates the early steering signal after a predetermined guard time which requires no external components. The delayed steering (DStD) will go high only when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD output will go low only after this validation period. Energy Detection The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal comparator (-35dBm), the energy detector produces an energy present indication on the SD output. The integrator ensures the SD output will remain at high even though the input signal is changing. When the input signal is removed, the SD output will go low following the integrator decay time. Short decay time enables the signal envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification. As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse applied at the ACK pin.

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