CDCM7005RGZT
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Manufacturer Part#:

CDCM7005RGZT

Product Category: Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Manufacturer: Texas Instruments
Description: IC CLK SYNC/JITTER CLEANER 48QFN
  datasheetCDCM7005RGZT Datasheet
Package: 48-VFQFN Exposed Pad
Quantity: 6064 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: Texas Instruments
Product Category: Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Series: CDCM7005
Type: Clock Synchronizer and Jitter Cleaner
Packaging: Digi-ReelR Alternate Packaging
Unit-Weight: 0.004868 oz
Mounting-Style: SMD/SMT
Package-Case: 48-VFQFN Exposed Pad
Operating-Temperature: -40°C ~ 85°C
Mounting-Type: Surface Mount
Voltage-Supply: 3 V ~ 3.6 V
Supplier-Device-Package: 48-VQFN (7x7)
PLL: Yes with Bypass
Input: LVCMOS, LVPECL
Output: LVCMOS, LVPECL
Number-of-Circuits: 1
Ratio-Input:Output: 1899/12/30 3:10:00
Differential-Input:Output: Yes/Yes
Frequency-Max: 1.5GHz
Divider-Multiplier: Yes/No
Number-of-Outputs: 5 Output
Maximum-Operating-Temperature: + 85 C
Minimum-Operating-Temperature: - 40 C
Operating-Supply-Current: 120 mA
Supply-Voltage-Max: 3.6 V
Supply-Voltage-Min: 3 V
Package-Case: VQFN-48
Maximum-Input-Frequency: 200 MHz
Max-Output-Freq: 1500 MHz
Output-Level: LVPECL
Input-Level: LVCMOS (REF CLK) LVPECL (VCXO CLK)
Features, Applications

3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

FEATURES

High Performance LVPECL and LVCMOS PLL Clock Synchronizer Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection Accepts LVCMOS Input Frequencies to 200 MHz VCXO_IN Clock is Synchronized to One of the Two Reference Clocks VCXO_IN Frequencies to 2.2 GHz (LVPECL) Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs to 10 LVCMOS Outputs) Output Frequency is Selectable x1, on Each Output Individually Efficient Jitter Cleaning From Low PLL Loop Bandwidth Low Phase Noise PLL Core Programmable Phase Offset (PRI_REF and SEC_REF to Outputs) Wide Charge Pump Current Range From 3 mA Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O Analog and Digital PLL Lock Indication Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN) Frequency Hold-Over Mode Improves Fail-Safe Operation Power-Up Control Forces LVPECL Outputs 3-State at VCC 1.5 V SPI Controllable Device Setting 3.3-V Power Supply Packaged in 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ) Industrial Temperature Range to 85°C


PRI_REF REF_SEL VCC_CP CP_OUT CTRL_LE CTRL_CLK




Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.


DESCRIPTION

The is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O: VC(X)O_IN / PRI_REF / M or VC(X)O_IN / SEC_REF / M VC(X)O_IN clock operates to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination up to five LVPECL outputs to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs Y1A:Y1B,...), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew. All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings. The device operates in 3.3-V environment and is characterized for operation from to 85°C.


PRI_REF R EF_MUX LVCMOS SEC_REF Progr. Delay M Progr. Divider M 2

÷3 LV CMOS ÷4 VCXO_IN PECL INPUT Y2_MUX LV PECL Y2B LV CMOS Y2A

Descriptions


Digikey
Search Part number : "CDCM7" Included word is 8
Part Number Manufacturer Package Quantity Description
CDCM7005RGZTG4 Texas Instruments 48-VFQFN Exposed Pad 2475 IC CLK SYNC/JITTER CLEANR 48VQFN
CDCM7005ZVA Texas Instruments 64-BGA 141 IC CLK SYNC/JITTER CLEANER 64BGA
CDCM7005ZVAR Texas Instruments 64-BGA 854 IC CLK SYNC/JITTER CLEANER 64BGA
CDCM7005ZVARG4 TI BGA 4410
CDCM7005ZVATG4 TI BGA 4287
CDCM7005HFG-V Ti 86
CDCM7005RG TI QFN 500
CDCM7005RGZT Ti 6064
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