DS33R11
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Manufacturer Part#:

DS33R11

Product Category: IC Chips
Manufacturer: Maxim Integrated
Description: IC ETHERNET MAPPER W/TXRX 256BGA
  datasheetDS33R11 Datasheet
Package: BGA256
Quantity: 895 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: Maxim Integrated
Product Category: IC Chips
Series: -
Type: Transceiver
Packaging: Tray
Package-Case: 256-BGA
Operating-Temperature: -40°C ~ 85°C
Mounting-Type: Surface Mount
Voltage-Supply: 1.8V, 3.3V
Supplier-Device-Package: 256-BGA (27x27)
Protocol: T1, E1, J1
Data-Rate: -
Number-of-Drivers-Receivers: -
Duplex: Full
Receiver-Hysteresis: -
Features, Applications

Features, Applications


The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream. The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) Controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33R11 can operate with an inexpensive external processor.


FEATURES

10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control Integrated T1/E1/J1 Framer and LIU HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments Programmable BERT for Serial (TDM) Interface External 16MB, 100MHz SDRAM Buffering Parallel Microprocessor Interface 1.8V, 3.3V Supplies Reference Design Routes on Two Signal Layers IEEE 1149.1 JTAG Support


APPLICATIONS

Transparent LAN Service LAN Extension Ethernet Delivery Over T1/E1/J1

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.


2 DESCRIPTION.................................................................................9 FEATURE HIGHLIGHTS........................................................................................ 11 2.1 GENERAL........................................................................................................... 11 2.2 MICROPROCESSOR INTERFACE............................................................................ 11 2.3 HDLC ETHERNET MAPPING.................................................................................... 2.4 X.86 (LINK ACCESS PROTOCOL FOR SONET/SDH) ETHERNET MAPPING.................................... 11 2.5 ADDITIONAL HDLC CONTROLLERS IN THE INTEGRATED T1/E1/J1 TRANSCEIVER.......................... 12 2.6 COMMITTED INFORMATION RATE (CIR) CONTROLLER.................................................................. 12 2.7 SDRAM INTERFACE......................................................................... 12 2.8 MAC INTERFACE.................................................................................................... 2.9 T1/E1/J1 LINE INTERFACE....................................................................... 13 2.10 CLOCK SYNTHESIZER................................................................................................ 13 2.11 JITTER ATTENUATOR.............................................................................. 2.12 T1/E1/J1 FRAMER................................................................................................. 14 2.13 TDM BUS......................................................................................... 14 2.14 TEST AND DIAGNOSTICS............................................................................................. 15 2.15 SPECIFICATIONS COMPLIANCE..................................................................................... 16 3 APPLICATIONS......................................................................................................... ACRONYMS AND GLOSSARY.................................................................................. 18 MAJOR OPERATING MODES................................................................ 19 BLOCK DIAGRAMS............................................................................. 20


PIN DESCRIPTIONS................................................................................................... 25 7.1 PIN FUNCTIONAL DESCRIPTION................................................................................... 25 8 FUNCTIONAL DESCRIPTION............................................................................ 41 8.1 PROCESSOR INTERFACE....................................................................................... 42


9.1.1 9.1.2 Ethernet Interface Clock Modes.....................................................................45 Serial Interface Clock Modes........................................................................................45


RESETS AND LOW POWER MODES......................................................................... 46 INITIALIZATION AND CONFIGURATION........................................................................ 47 GLOBAL RESOURCES......................................................................................... 47 PER-PORT RESOURCES............................................................................................. 47 DEVICE INTERRUPTS........................................................................................ 48 INTERRUPT INFORMATION REGISTERS...................................................................... 50 STATUS REGISTERS..................................................................................................... 50 INFORMATION REGISTERS........................................................................................ 50 SERIAL INTERFACE.................................................................................................... 50 CONNECTIONS AND QUEUES................................................................................... 51 ARBITER................................................................................................................... 52 FLOW CONTROL...............................................................................

9.13.1 Full Duplex Flow Control.....................................................................................................................54 9.13.2 Half Duplex Flow Control.....................................................................................................................55 9.13.3 Host-Managed Flow of 338


Receive Data Interface........................................................................................................................63 Repetitive Pattern Synchronization.....................................................................................................64 Pattern Monitoring...............................................................................................................................64 Pattern Generation..............................................................................................................................64


9.17 TRANSMIT PACKET PROCESSOR................................................................................................ 65 9.18 RECEIVE PACKET PROCESSOR.................................................................................................. 9.19 X.86 ENCODING AND DECODING................................................................................................ 68 9.20 COMMITTED INFORMATION RATE CONTROLLER............................................................. 71 10 INTEGRATED T1/E1/J1 TRANSCEIVER..................................................................................... 10.1 T1/E1/J1 CLOCKS.................................................................................................................... 72 10.2 PER-CHANNEL OPERATION........................................................................................................ 10.3 T1/E1/J1 TRANSCEIVER INTERRUPTS........................................................................................ 10.4 T1 FRAMER/FORMATTER CONTROL AND STATUS........................................................... 74


10.4.1 T1 Transmit Transparency...............................................................................74 10.4.2 AIS-CI and RAI-CI Generation and 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation................................................................75


Line-Code Violation Counter (TR.LCVCR).....................................................................78 Path Code Violation Count Register (TR.PCVCR)................................................79 Frames Out-of-Sync Count Register (TR.FOSCR)............................................................80 E-Bit Counter (TR.EBCR)....................................................................

Processor-Based Receive Signaling.................................................................82 Hardware-Based Receive Signaling...................................................................................83 Processor-Based Transmit Signaling.........................................................84 Hardware-Based Transmit Signaling.....................................................................................85


10.11 CHANNEL BLOCKING REGISTERS....................................................... 88 10.12 ELASTIC STORES OPERATION............................................................................... 88


10.12.1 Receive Elastic Store..................................................................................88 10.12.2 Transmit Elastic Store............................................................89 10.12.3 Elastic Stores Initialization................................................................89 10.12.4 Minimum Delay Mode....................................................

10.13 G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)........................................ 10.14 T1 BIT-ORIENTED CODE (BOC) CONTROLLER...................................................... 91


10.15 RECEIVE BOC......................................................................... 91 10.16 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)........................................ 92


10.16.1 Method 1: Internal Register Scheme Based Double-Frame.............................92 10.16.2 Method 2: Internal Register Scheme Based CRC4 Multiframe......................................................92 



Search Part number : "DS33R" Included word is 2
Part Number Manufacturer Package Quantity Description
DS33R11+ Maxim Integrated BGA-256 2135 IC ETH TXRX T1/E1/J1 256-BGA
DS33R41 Maxim Integrated 400-BGA 530 IC INVERSE-MUX ETH MAPPER 400BGA
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