DS26334G+
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Manufacturer Part#:

DS26334G+

Product Category: IC Chips
Manufacturer: Maxim Integrated
Description: IC SLIC 16CH 256CSBGA
  datasheetDS26334G+ Datasheet
Package: CSBGA256
Quantity: 155 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: Maxim Integrated
Product Category: IC Chips
Series: DS26334G
Product: LIU - Line Interface Units
Type: E1/T1/J1 Long Haul/Short Haul LIU
Packaging: Tray
Mounting-Style: SMD/SMT
Package-Case: 256-LBGA, CSBGA
Operating-Temperature: 0°C ~ 70°C
Mounting-Type: Surface Mount
Function: Line Interface Unit (LIU)
Interface: LIU
Voltage-Supply: 3.135 V ~ 3.465 V
Supplier-Device-Package: 256-CSBGA (17x17)
Number-of-Circuits: 16
Power-Watts: -
Current-Supply: 500mA
Maximum-Operating-Temperature: + 70 C
Minimum-Operating-Temperature: 0 C
Operating-Supply-Voltage: 3.3 V
Operating-Supply-Current: 500 mA
Interface-Type: LIU
Part-#-Aliases: 90-26334+G00
Supply-Voltage-Max: 3.465 V
Supply-Voltage-Min: 3.135 V
Package-Case: CSBGA-256
Features, Applications

Features, Applications


The a 16-channel short/long-haul line interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A single bill of material can support E1/T1/J1 that requires no external termination. Redundancy is supported through nonintrusive monitoring, optimal high-impedance modes and configurable or 1+1 backup enhancements. An on-chip synthesizer generates the E1/T1/J1 clock rates by a single master clock input of various frequencies. Two clock output references are also offered. The device is offered a 256-pin TE-CSBGA, the smallest package available for a 16-channel LIU.


FEATURES

or J1 Short/Long-Haul Line Interface Units Independent or J1 Selections Fully Internal Impedance Match Requires No External Resistors Software-Selectable Transmit and ReceiveSide Impedance Match Crystal-Less Jitter Attenuator Selectable Single-Rail and Dual-Rail Mode and AMI or HDB3/B8ZS Line Encoding and Decoding Detection and Generation of AIS Digital/Analog Loss of Signal Detection as per T1.231, G.775 and ETS 300 233 External Master Clock Can Be Multiple or 1.544MHz for or E1 Operation; This Clock Will Be Internally Adapted for or E1 Usage Receiver Signal Level Indicator from in T1 Mode and in E1 Mode in 2.5dB Increments Two Built-In BERT Testers for Diagnostics 8-Bit Parallel Interface Support for Intel or Motorola Mode a 4-Wire Serial Interface Transmit Short-Circuit Protection G.772 Nonintrusive Monitoring Receive Monitor Mode Handles Combinations 30dB of Resistive Attenuation Along with 30dB of Cable Attenuation Specification Compliance to the Latest T1 and E1 Standards Single 3.3V Supply with 5V Tolerant I/O JTAG Boundary Scan as Per IEEE 1149.1


APPLICATIONS

T1 Digital Cross-Connects ATM and Frame Relay Equipment Wireless Base Stations ISDN Primary Rate Interface E1/T1/J1 Multiplexer and Channel Banks E1/T1/J1 LAN/WAN Routers


RPOS RNEG RCLK TPOS TNEG TCLK

PART DS26334GN DS26334GN+ TEMP RANGE PIN-PACKAGE +85°C 256 TE-CSBGA 256 TE-CSBGA 256 TE-CSBGA 256 TE-CSBGA


Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.


1 STANDARDS COMPLIANCE........................................................................................................ 6 1.1 TELECOM SPECIFICATIONS COMPLIANCE....................................................................................... 6 2 DETAILED DESCRIPTION............................................................................................................ BLOCK DIAGRAMS...................................................................................................................... 8 PIN DESCRIPTION...................................................................................................................... 10 FUNCTIONAL DESCRIPTION..................................................................................................... 17 5.1 PORT OPERATION...................................................................................................................... 17


5.1.2 5.1.3 Serial Port Operation..................................................................................................................... 17 Parallel Port Operation................................................................................................................... 18 Interrupt Handling.......................................................................................................................... 18


Transmit Line Templates................................................................................................................ 22 LIU Transmit Front-End.................................................................................................................. 25 Transmit Dual-Rail Mode............................................................................................................... 26 Transmit Single-Rail Mode............................................................................................................. 26 Zero HDB3................................................................................................ 26 Transmit Power-Down.................................................................................................................... 26 Transmit All Ones.......................................................................................................................... 27 Driver Fail Monitor.......................................................................................................................... 27 Receiver Impedance Matching Calibration..................................................................................... 27 Receiver Monitor Mode.................................................................................................................. 27 Peak Detector and Slicer............................................................................................................... 28 Receive Level Indicator.................................................................................................................. 28 Clock and Data Recovery............................................................................................................... 28 Loss of Signal................................................................................................................................ 28 AIS................................................................................................................................................ 29 Receive Dual-Rail Mode................................................................................................................ 30 Receive Single-Rail Mode.............................................................................................................. 30 Bipolar Violation and Excessive Zero Detector............................................................................... 30


Analog Loopback........................................................................................................................... 32 Digital Loopback............................................................................................................................ 33 Remote Loopback.......................................................................................................................... 33 General Description....................................................................................................................... 34 Configuration and Monitoring......................................................................................................... 35 Receive Pattern Detection.............................................................................................................. 36 Transmit Pattern Generation.......................................................................................................... 38


Primary Register Bank................................................................................................................... 48 Secondary Register Bank............................................................................................................... 63 Individual LIU Register Bank.......................................................................................................... 66 BERT Registers............................................................................................................................. 85


JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.................................. 92 7.1 TAP CONTROLLER STATE MACHINE............................................................................................ 93


DC ELECTRICAL CHARACTERIZATION................................................................................... 8.1 DC PIN LOGIC LEVELS................................................................................................................ 98 8.2 SUPPLY CURRENT AND OUTPUT VOLTAGE................................................................................... 9 AC TIMING CHARACTERISTICS................................................................................................ 99 9.1 LINE INTERFACE CHARACTERISTICS............................................................................................ 99 9.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS...............................................................100 9.3 SERIAL PORT............................................................................................................................112 9.4 SYSTEM TIMING........................................................................................................................113 9.5 JTAG TIMING............................................................................................................................115 10 PIN 12 13 PACKAGE INFORMATION.........................................................................................................117 THERMAL INFORMATION.........................................................................................................118 DATA SHEET REVISION HISTORY...........................................................................................120  



Search Part number : "DS263" Included word is 8
Part Number Manufacturer Package Quantity Description
DS26334GN+ Maxim Integrated 256CSBGA 91 IC SLIC 16CH 256CSBGA
DS26334GNA3 Maxim Integrated 256-LBGA, CSBGA 76 IC LIU T1/E1/J1 256CSBGA
DS26303-120 DALLAS TQFP144 1120
DS26303LN-75+ Maxim Integrated 144-LQFP Exposed Pad 72 IC LIU E1/T1/J1 3.3V 144-ELQFP
DS26324 DALLAS BGA 668
DS26324GN Maxim Integrated 256-LBGA, CSBGA 78 IC LIU T1/E1/J1 256CSBGA
DS26324GN+ Maxim Integrated 256-LBGA, CSBGA 144 IC LIU 16CH T1/E1/J1 256CSBGA
DS26324GNA2+ Maxim Integrated BGA256 852 IC SLIC 16CH 256CSBGA
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