ADSP-2191MKST-160
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ADSP-2191MKST-160

Product Category: IC Chips
Manufacturer: ADI
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  datasheetADSP-2191MKST-160 Datasheet
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Manufacturer: ADI
Product Category: IC Chips
Features, Applications


Performance Features

6.25 ns Instruction Cycle Time, for to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic Syntax Single-Cycle Instruction Execution Single-Cycle Context Switch between Two Sets of Computation and Memory Instructions Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle

Multifunction Instructions Pipelined Architecture Supports Efficient Code Execution Architectural Enhancements for Compiled C and C++ Code Efficiency Architectural Enhancements beyond ADSP-218x Family are Supported with Instruction Set Extensions for Added Registers, and Peripherals Flexible Power Management with User-Selectable Power-Down and Idle Modes

24 BIT ADDRESS DATA 24 BIT ADDRESS DATA 16 BIT DATA ADDRESS 16 BIT DATA ADDRESS

PROGRAM SEQUENCER EXTERNAL PORT PM ADDRESS BUS 24 I/O ADDRESS 18 ADDR BUS MUX 24 DMA CONNECT PM DATA BUS 24 16 I/O DATA I/O PROCESSOR DATA BUS MUX 16 DMA ADDRESS 24 DMA DATA 22

DATA REGISTER FILE INPUT REGISTERS RESULT REGISTERS MULT 16 16-BIT BARREL SHIFTER ALU I/O REGISTERS (MEMORY-MAPPED) CONTROL STATUS BUFFERS DMA CONTROLLER

24 HOST PORT 18 SERIAL PORTS (3) 6 SPI PORTS (2) 2 UART PORT (1) 3 SYSTEM INTERRUPT CONTROLLER PROGRAMMABLE FLAGS (16) TIMERS (3)

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 c Analog Devices, Inc., 2002

INTEGRATION FEATURES 160 K Bytes On-Chip RAM Configured as 32K Words 24-Bit Memory RAM and 32K Words 16-Bit Memory RAM Dual-Purpose 24-Bit Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-bit Accumulators Unified Memory Space Allows Flexible Address Generation, Using Two Independent DAG Units Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution Enhanced Interrupt Controller Enables Programming of Interrupt Priorities and Nesting Modes SYSTEM INTERFACE FEATURES Host Port with DMA Capability for Glueless or 16-Bit Host Interface 16-Bit External Memory Interface for to 16M Words of Addressable Memory Space Three Full-Duplex Multichannel Serial Ports, with Support for H.100 and to 128 TDM Channels with A-Law and -Law Companding Optimized for Telecommunications Systems Two SPI-Compatible Ports with DMA Support UART Port with DMA Support 16 General-Purpose I/O Pins with Integrated Interrupt Support Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulsewidth Measurement, and External Event Counter Capabilities to 11 DMA Channels Can Be Active at Any Given Time for High I/O Throughput On-Chip Boot ROM for Automatic Booting from External or 16-Bit Host Device, SPI ROM, or UART with Autobaud Detection Programmable PLL Supports to 32 Input Frequency Multiplication and Can Be Altered during Runtime IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 2.5 V Internal Operation and 3.3 V I/O 144-Lead LQFP and 144-Ball Mini-BGA Packages TABLE OF CONTENTS

GENERAL DESCRIPTION.3 DSP Core Architecture.3 DSP Peripherals Architecture.4 Memory Architecture.5 Interrupts.6 DMA Controller.7 Host Port.8 DSP Serial Ports (SPORTs).9 Serial Peripheral Interface (SPI) Ports.9 UART Port. 9 Programmable Flag (PFx) Pins.10 Low Power Operation.10 Clock Signals.11 Reset.11 Power Supplies.11 Booting Modes.11 Bus Request and Bus Grant.12 Instruction Set Description.13 Development Tools.13 Additional Information.15 PIN FUNCTION DESCRIPTIONS.15 SPECIFICATIONS. 18 ABSOLUTE MAXIMUM RATINGS. 19 ESD SENSITIVITY.19 Power Dissipation.19 TIMING SPECIFICATIONS.20 Output Drive Currents.41 Power Dissipation.41 Test Conditions.41 Environmental Conditions.42 144-Lead LQFP Pinout.44 144-Lead Mini-BGA Pinout.46 OUTLINE DIMENSIONS.48 ORDERING GUIDE.49

The ADSP-2191M DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2191M combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces. The ADSP-2191M architecture is code-compatible with DSPs of the ADSP-218x family. Although the architectures are compatible, the ADSP-2191M architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2191M more flexible and even easier to program. Indirect addressing options provide addressing flexibility-- premodify with no update, pre- and post-modify by an immediate 8-bit, two's-complement value and base address registers for easier implementation of circular buffering. The ADSP-2191M integrates 64K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 32K words (16-bit) of data RAM. Power-down circuitry is also provided to reduce power consumption. The ADSP-2191M is available in 144-lead LQFP and 144-ball mini-BGA packages. Fabricated in a high-speed, low-power, CMOS process, the ADSP-2191M operates with 6.25 ns instruction cycle time (160 MIPS). All instructions, except single-word instructions, execute in one processor. The ADSP-2191M's flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, the ADSP-2191M can: Generate an address for the next instruction fetch Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation These operations take place while the processor continues to: Receive and transmit data through two serial ports Receive and/or transmit data from a Host Receive or transmit data through the UART Receive or transmit data over two SPI ports Access external memory through the external memory interface Decrement the timers

uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The functional block diagram on page 1 shows the architecture of the ADSP-219x core. It contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations. The MAC has two 40-bit accumulators, which help with overflow. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. Register-usage rules influence placement of input and results within the computational units. For most operations, the computational units' data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. For more information, see the ADSP-219x DSP Instruction Set Reference. A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-2191M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing within 64K word boundaries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and secondary registers provides a fast context switch. Efficient data transfer in the core is achieved with the use of internal buses: Program Memory Address (PMA) Bus Program Memory Data (PMD) Bus Data Memory Address (DMA) Bus Data Memory Data (DMD) Bus DMA Address Bus DMA Data Bus

The ADSP-2191M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2191M assembly language REV. 0 -3-.




Search Part number : "ADSP-" Included word is 15
Part Number Manufacturer Package Quantity Description
ADSP-21MSP58BST-104 advics QFP 78
ADSP-BF531BST400 ADI QFP 71
ADSP-BF533SKBCZ400 ADI 4060
ADSP-BF561SKBCZ600 ADI BGA 514
ADSP-BF531SBBC400 Analog Devices Inc. 160-LFBGA, CSPBGA 7431 IC DSP CTLR 16B 400MHZ 160MBGA
ADSP-BF518BSWZ-4F4 Analog Devices Inc. 176-LQFP Exposed Pad 126 IC DSP 16/32B 400MHZ LP 176LQFP
ADSP-2183KSTZ-210 Analog Devices Inc. 128-LQFP 459 IC DSP CONTROLLER 16BIT 128-LQFP
ADSP-BF561SKBCZ-6A Analog Devices Inc. 256-BGA, CSPBGA 158 IC DSP CTRLR 32B 600MHZ 256CPBGA
ADSP-21369KBPZ-2A Analog Devices Inc. 256-LBGA Exposed Pad 3245 IC DSP 32BIT 333MHZ 256-BGA
ADSP-21363BSWZ-1AA Analog Devices Inc. 144-LQFP Exposed Pad 506 IC DSP 32BIT 333MHZ EPAD 144LQFP
ADSP-2191MKSTZ-160 Analog Devices Inc. 144-LQFP 72 IC DSP CONTROLLER 16BIT 144LQFP
ADSP-TS201SABPZ-060 ADI 576-BBGA Exposed Pad 558 IC PROCESSOR 600MHZ 576BGA
ADSP-21262SKBCZ200 Analog Devices Inc. 136-LFBGA, CSPBGA 1182 IC DSP CTLR 32BIT 136CSPBGA
ADSP-TS101SAB1Z-000 ADI 625-BBGA 159 IC DSP CONTROLLER 6MBIT 625-BGA
ADSP-2185NKSTZ-320 Analog Devices Inc. 100-LQFP 511 IC DSP CONTROLLER 16BIT 100LQFP
ADSP-2191MKST-160 RELATED PRODUCT PICTURE
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  • ADSP-21MSP58BST-104
  • ADSP-BF531BST400
  • ADSP-BF533SKBCZ400
  • ADSP-BF561SKBCZ600
  • ADSP-BF531SBBC400
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  • ADSP-2183KSTZ-210
  • ADSP-BF561SKBCZ-6A
  • ADSP-21369KBPZ-2A
  • ADSP-21363BSWZ-1AA
  • ADSP-2191MKSTZ-160
  • ADSP-TS201SABPZ-060
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  • ADSP-2185NKSTZ-320
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