ADSP-2186LBST-133
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ADSP-2186LBST-133

Product Category: IC Chips
Manufacturer: ADI
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  datasheetADSP-2186LBST-133 Datasheet
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Quantity: 651 PCS
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Manufacturer: ADI
Product Category: IC Chips
Features, Applications

Features

Performance 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 400 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode

POWER-DOWN CONTROL MEMORY 8K 16 PROGRAM DATA MEMORY PROGRAMMABLE I/O AND FLAGS FULL MEMORY MODE EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER

PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA

EXTERNAL DATA BUS ARITHMETIC UNITS SERIAL PORTS SPORT 0 SPORT 1 TIMER INTERNAL DMA PORT HOST MODE ALU MAC SHIFTER

Integration ADSP-2100 Family Code Compatible, with Instruction Set Extensions 40K Bytes of On-Chip RAM, Configured as 8K Words On-Chip Program Memory RAM and 8K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA System Interface 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory (Mode Selectable) 4 MByte Byte Memory Interface for Storage of Data Tables and Program Overlays 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits "Glueless" System Design (Mode Selectable) Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port Six External Interrupts

13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-PortTM Emulator Interface Supports Debugging in Final Systems GENERAL DESCRIPTION

The is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2186L combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2186L integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2186L is available a 100-lead LQFP and 144-ball mini-BGA packages. In addition, the ADSP-2186L supports new instructions, which include bit manipulations--bit set, bit clear, bit toggle, bit test-- new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2186L operates with 25 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-21xx family DSPs contain a shadow bank register that is useful for single cycle context switching of the processor.

ICE-Port is a trademark of Analog Devices, Inc. All other trademarks are the property of their respective holders.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 c Analog Devices, Inc., 2001

The ADSP-2186L's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2186L can: Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation This takes place while the processor continues to: Receive and transmit data through the two serial ports Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Decrement timer

PC upload and download functions Instruction-level emulation of program booting and execution Complete assembly and disassembly of instructions C source-level debugging

See Designing An EZ-ICE-Compatible Target System in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as well as the Target Board Connector for EZ-ICE Probe section of this data sheet, for the exact specifications of the EZ-ICE target board connector.

The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2186L. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an executable file. The Simulator provides an interactive instruction- level simulation with a reconfigurable user interface to display different portions of the hardware environment. A PROM Splitter generates PROM programmer compatible files. The C Compiler, based on the Free Software Foundation's GNU C Compiler, generates ADSP-2186L assembly source code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 ANSI-standard mathematical and DSP-specific functions. The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the ADSP-218x family: an ADSP218x-based evaluation board with PC monitor software plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low-cost, easy-to-use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: 75 MHz ADSP-2189M Full 16-bit Stereo Audio I/O with AD73322 Codec RS-232 Interface EZ-ICE Connector for Emulator Control DSP Demo Programs Evaluation Suite of Visual DSP The ADSP-218x EZ-ICE Emulator aids in the hardware debugging an ADSP-2186L system. The emulator consists of hardware, host computer resident software, and the target board connector. The ADSP-2186L integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-2186L device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. The EZ-ICE performs a full range of functions, including: In-target operation to 20 breakpoints Single-step or full-speed operation Registers and memory values can be examined and altered

SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc.

This data sheet provides a general overview of ADSP-2186L functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-218x DSP Hardware Reference. For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.

The ADSP-2186L instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2186L assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

POWER-DOWN CONTROL DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY 8K 16 PROGRAM DATA MEMORY PROGRAMMABLE I/O AND FLAGS

FULL MEMORY MODE EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER

EXTERNAL DATA BUS ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT 0 SPORT 1 TIMER INTERNAL DMA PORT HOST MODE

Figure is an overall block diagram of the ADSP-2186L. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. The internal result (R) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle.

The ADSP-2186L is available a 100-lead LQFP and a 144-ball Mini-BGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.

Search Part number : "ADSP-" Included word is 15
Part Number Manufacturer Package Quantity Description
ADSP-2189MBST-266 AD QFP 720
ADSP-2191MKST-160 ADI TQFP 532
ADSP-21MSP58BST-104 advics QFP 78
ADSP-BF531BST400 ADI QFP 71
ADSP-BF533SKBCZ400 ADI 4060
ADSP-BF561SKBCZ600 ADI BGA 514
ADSP-BF531SBBC400 Analog Devices Inc. 160-LFBGA, CSPBGA 7431 IC DSP CTLR 16B 400MHZ 160MBGA
ADSP-BF518BSWZ-4F4 Analog Devices Inc. 176-LQFP Exposed Pad 126 IC DSP 16/32B 400MHZ LP 176LQFP
ADSP-2183KSTZ-210 Analog Devices Inc. 128-LQFP 459 IC DSP CONTROLLER 16BIT 128-LQFP
ADSP-BF561SKBCZ-6A Analog Devices Inc. 256-BGA, CSPBGA 158 IC DSP CTRLR 32B 600MHZ 256CPBGA
ADSP-21369KBPZ-2A Analog Devices Inc. 256-LBGA Exposed Pad 3245 IC DSP 32BIT 333MHZ 256-BGA
ADSP-21363BSWZ-1AA Analog Devices Inc. 144-LQFP Exposed Pad 506 IC DSP 32BIT 333MHZ EPAD 144LQFP
ADSP-2191MKSTZ-160 Analog Devices Inc. 144-LQFP 72 IC DSP CONTROLLER 16BIT 144LQFP
ADSP-TS201SABPZ-060 ADI 576-BBGA Exposed Pad 558 IC PROCESSOR 600MHZ 576BGA
ADSP-21262SKBCZ200 Analog Devices Inc. 136-LFBGA, CSPBGA 1182 IC DSP CTLR 32BIT 136CSPBGA
ADSP-2186LBST-133 RELATED PRODUCT PICTURE
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  • ADSP-2189MBST-266
  • ADSP-2191MKST-160
  • ADSP-21MSP58BST-104
  • ADSP-BF531BST400
  • ADSP-BF533SKBCZ400
  • ADSP-BF561SKBCZ600
  • ADSP-BF531SBBC400
  • ADSP-BF518BSWZ-4F4
  • ADSP-2183KSTZ-210
  • ADSP-BF561SKBCZ-6A
  • ADSP-21369KBPZ-2A
  • ADSP-21363BSWZ-1AA
  • ADSP-2191MKSTZ-160
  • ADSP-TS201SABPZ-060
  • ADSP-21262SKBCZ200
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