CY25561SXC-TBB
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CY25561SXC-TBB

Product Category: IC Chips
Manufacturer: CYPRESS
Description:
  datasheetCY25561SXC-TBB Datasheet
Package: SOP-8
Quantity: 1207 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: CYPRESS
Product Category: IC Chips
Features, Applications

Features,Applications

to 166 MHz Operating Frequency Range Wide Range of Spread Selections:9 Accepts Clock and Crystal Inputs Low Power Dissipation 70 mW-Typ at 66 MHz Frequency Spread Disable Function Center Spread Modulation Low Cycle-to-cycle Jitter 8-pin SOIC Package


Desktop, notebook, and tablet PCs VGA controllers LCD panels and monitors Workstations and servers

Peak EMI reduction to16 dB Fast time to market Cost reduction

Cypress Semiconductor Corporation Document Number: 38-07242 Rev. *C

Table 1. Pin Description Pin Name Xin/CLK VDD GND SSCLK SSCC S1

Type Positive power supply Power supply ground Modulated clock output

Description Clock or crystal connection input. Refer to Table 2 for input frequency range selection.


Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input is high and disabled when input is low. This pin is pulled high internally. Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth selection and tri-level logic programming. See Figure 2. Pin 6 has internal resistor divider network to VDD and VSS. Refer to Logic Block Diagram on page 1. Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth selection and tri-level logic programming. See Figure 2. Pin 7 has internal resistor divider network to VDD and VSS. Refer to Logic Block Diagram on page 1. Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock drives Xin/CLK.


is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic Interference (EMI) found in today's high speed digital electronic systems. CY25561 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading the system performance. is a very simple and versatile device to use. The frequency and spread percentage range is selected by programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic levels to select one of the nine available spread percentage ranges. Refer to Table 2 for programming details. CY25561 is intended for use with applications with a reference frequency in the range to 166 MHz. A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 and S1 digital control inputs. The output spread (frequency modulation) is symmetrically centered on the input frequency. Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing. CY25561 is available in an eight-pin SOIC package with to 70°C operating temperature range.


Note: Refer to the CY25560 data sheet for operation at frequencies from 25 to100 MHz.

Table 2. Frequency and Spread Percentage Selection (Center Spread)

Se lect the Frequenc y and Center Spr ead % desir ed and then set S 1, indicated.

Se lect the Frequenc y and Center Spr ead % desir ed and then set S 1, indicated.

With binary logic, four states can be programmed with two control lines, whereas tri-level logic can program nine logic states using two control lines. Tri-level logic CY25561 is implemented by defining a third logic state in addition to the standard logic "1" and "0". Pins 6 and of CY25561 recognize a logic state by the voltage applied to the respective pin. These states are defined as "0" (low), "M" (middle), and "1" (one). Each of these states has a defined voltage range that is interpreted a "0," "M," or "1" logic state. Refer to Table 3 for voltage ranges for each logic state. CY25561 has two equal value resistors connected internally to pin 6 and pin 7 that produce the default "M" state. Pins 6 and/or 7 can be tied directly to ground or VDD to program a logic or "1" state, respectively. Refer to Figure 2 for examples. Figure 2. Tri-level Logic Examples

Search Part number : "CY255" Included word is 13
Part Number Manufacturer Package Quantity Description
CY25562SXC Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 94 IC CLOCK GEN 3.3V SS 8-SOIC
CY25568SXCT Cypress Semiconductor Corp 16-SOIC (0.154", 3.90mm Width) 3054 IC CLOCK GEN 3.3V SS 16SOIC
CY25560SC CY SOP-8 611
CY25560SXC Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 3900 IC CLOCK GEN 3.3V SS 8-SOIC
CY25560-SXC CYTRESS SOP8 161
CY25560SXCT Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 27776 IC CLOCK GEN 3.3V SS 8-SOIC
CY25560SXC-T CYPREE 8-SOIC (0.154", 3.90mm Width) 1150 IC CLOCK GEN 3.3V SS 8-SOIC
CY25560-SXI CY SOP8 3692
CY25560SXIT Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 9060 IC CLOCK GEN 3.3V SS 8-SOIC
CY25561-SC CY SOP8 96500
CY25561SXC Cypress Semiconductor Corp 8-SOIC (0.154", 3.90mm Width) 88 IC CLOCK GEN 3.3V SS 8-SOIC
CY25561-SC CYPRESS 96500
CY25561SXCT Cypress Semiconductor Corp SOP-8 2464 IC CLOCK GEN 3.3V SS 8-SOIC
CY25561SXC-TBB RELATED PRODUCT PICTURE
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  • CY25562SXC
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  • CY25560SC
  • CY25560SXC
  • CY25560-SXC
  • CY25560SXCT
  • CY25560SXC-T
  • CY25560-SXI
  • CY25560SXIT
  • CY25561-SC
  • CY25561SXC
  • CY25561-SC
  • CY25561SXCT
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