MT48LC8M16A2P-6AL
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MT48LC8M16A2P-6AL

Product Category: IC Chips
Manufacturer: MICRON
Description:
  datasheetMT48LC8M16A2P-6AL Datasheet
Package: TSOP54
Quantity: 71 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Moisture Sensitivity Level(MSL): 3(168 Hours)
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Manufacturer: MICRON
Product Category: IC Chips
Features, Applications

For the latest data sheet, refer to Micron's Web site: www.micron.com

Features

PC100- and PC133-compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths (BL): or full page Auto precharge, includes concurrent auto precharge, and auto refresh modes Self refresh mode; standard and low power 64ms, 4,096-cycle refresh (commercial & industrial) 16ms, 4,096-cycle refresh (Automotive) LVTTL-compatible inputs and outputs Single +3.3 ±0.3V power supply


Options

Configurations - 32 Meg 4 (8 Meg banks) - 16 Meg 8 (4 Meg banks) - 8 Meg 16 (2 Meg x 4 banks) Write recovery (tWR) - tWR "2 CLK"1 Package/Pinout - Plastic package - 54-pin TSOP II (400 mil) - 54-pin TSOP II (400 mil) Pb-free - 60-ball FBGA - 60-ball FBGA x 16mm) Pb-free - 54-ball VFBGA - 54-ball VFBGA x 8mm) Pb-free Timing (cycle time) 3 (x16 only) Self refresh - Standard - Low power Design revision Operating temperature range - Commercial +70°C) - Industrial +85°C) - Automotive to +105°C)


Notes: Refer to Micron technical note: TN-48-05. Off-center parting line. Consult Micron for availability. x16 only.


VDD DQ0 - VDDQ DQ2 - VssQ DQ4 - VDDQ DQ6 - VssQ NC DQ7 VDD NC DQML - WE# - CAS# - RAS# CS# A2 A3 VDD -


1. The # symbol indicates signal is active LOW. A dash indicates x8 and x4 pin function is same as x16 pin function.


Configuration Refresh count Row addressing Bank addressing Column addressing

Micron Technology, Inc., reserves the right to change products or specifications without notice. c1999 Micron Technology, Inc. All rights reserved.


Products and specifications discussed herein are subject to change by Micron without notice.

The MicronR 128Mb SDRAM is a high-speed CMOS, dynamic random access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4's 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns by 4 bits. Each of the x8's 33,554,432-bit banks is organized as 4,096 rows by 1,024 columns by 8 bits. Each of the x16's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.


The automotive temperature (AT) option adheres to the following specifications: 16ms refresh rate Self refresh not supported Ambient and case temperature cannot be less than -40°C or greater than +105°C


Search Part number : "MT48L" Included word is 15
Part Number Manufacturer Package Quantity Description
MT48LC32M16A2P-75C MICRON TSOP 2593
MT48LC4M32B2P-7IT:G MICRON TSOP86 2133
MT48LC4M32B2P-6 G MICRON TSSOP 496
MT48LC8M16A2 MICRON TSOP 882
MT48LC8M32B2F5-7IT MICRON FBGA90 457
MT48LC32M8A2TG-75 MT TSOP 167
MT48LC64M4A2BB-75D MICRON BGA 725
MT48LC2M32B2P-7 IT:G Micron Technology Inc. 86-TFSOP (0.400", 10.16mm Width) 1640 IC SDRAM 64MBIT 143MHZ 86TSOP
MT48LC4M32B2P-6:G Micron Technology Inc. 86-TFSOP (0.400", 10.16mm Width) 7397 IC SDRAM 128MBIT 167MHZ 86TSOP
MT48LC8M32B2P-6 MICRON 86-TFSOP (0.400", 10.16mm Width) 1200 IC SDRAM 256MBIT 166MHZ 86TSOP
MT48LC16M8A2P-75:G Micron Technology Inc. 54-TSOP (0.400", 10.16mm Width) 59948 IC SDRAM 128MBIT 133MHZ 54TSOP
MT48LC32M8A2TG-75 IT:D Micron Technology Inc. 54-TSOP (0.400", 10.16mm Width) 72 IC SDRAM 256MBIT 133MHZ 54TSOP
MT48LC4M16A2P-75 ITG MICRON 54-TSOP (0.400", 10.16mm Width) 515 IC SDRAM 64MBIT 133MHZ 54TSOP
MT48LC16M16A2 MICRONA TSOP 3130
MT48LC16M16A2B4-7EIT:G MICRON FBGA 1263
MT48LC8M16A2P-6AL RELATED PRODUCT PICTURE
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